硬件描述语言范例
来源：入团申请书 发布时间：2020-09-12 点击：
硬件描述语言语言设计实例
1、8-3编码器
module encode_verilog ( a ,b );
input [7:0] a ; //编码器输入wire [7:0] a ;
output [2:0] b ; //编码器输出reg [2:0] b;
always @ ( a )
begin
case ( a ) //编码器端口高电平输出二进制数 8'b0000_0001 : b<=3'b000; //0
8'b0000_0010 : b<=3'b001; //1
8'b0000_0100 : b<=3'b010; //2
8'b0000_1000 : b<=3'b011; //3
8'b0001_0000 : b<=3'b100; //4
8'b0010_0000 : b<=3'b101; //5
8'b0100_0000 : b<=3'b110; //6
8'b1000_0000 : b<=3'b111; //7
default : b<= 3'b000; //其他情况编码器输出’b000
endcase
end
endmodule
2、8-3优先编码器
module p_encode_verilog ( A ,I ,GS ,EO ,EI ); //编码器低有效input [7:0] I ; //编码器输入wire [7:0] I ;
input EI ; //输入使能=0时，器正常工作wire EI ;
output [2:0] A ; //编码器输出reg [2:0] A ;
output GS ; //优先编码器工作状态器八个输入端输入时，GS0
reg GS ;
output EO ; //输出使能reg EO ;
always @ ( I or EI )
if ( EI ) //使用if、else if表的优先级顺序 begin
A <= 3'b111;
GS <= 1;
EO <= 1;
end
else if ( I[7] == 0 )
begin
A <= 3'b000;
GS <= 0;
EO <= 1;
end
else if ( I[6] == 0 )
begin
A <= 3'b001;
GS <= 0;
EO <= 1;
end
else if ( I[5] == 0 )
begin
A <= 3'b010;
GS <= 0;
EO <= 1;
end
else if ( I[4] == 0 )
begin
A <= 3'b011;
GS <= 0;
EO <= 1;
end
else if ( I[3] == 0 )
begin
A <= 3'b100;
GS <= 0;
EO <= 1;
end
else if ( I[2] == 0 )
begin
A <= 3'b101;
GS <= 0;
EO <= 1;
end
else if ( I[1] == 0 )
begin
A <= 3'b110;
GS <= 0;
EO <= 1;
end
else if ( I[0] == 0 )
begin
A <= 3'b111;
GS <= 0;
EO <= 1;
end
else if ( I == 8'
begin
A <= 3'b111;
GS <= 1;
EO <= 0;
end
endmodule
3、3-8译码器
module decoder_verilog ( G1 ,Y ,G2 ,A ,G3 );
input G1 ; //使能输入，高有效wire G1 ;
input G2 ; //使能输入低有效wire G2 ;
input [2:0] A ; //3位译码器输入，为高有效wire [2:0] A ;
input G3 ; //使能输入wire G3 ; //使能输入低有效
output [7:0] Y ; //8译码器输出，为有效reg [7:0] Y ;
reg s;
always @ ( A ,G1, G2, G3)
begin
s <= G2 | G3 ;
if ( G1 == 0) //G1为低有效 Y <= 8'b1111_1111;
else if ( s)
Y <= 8'b1111_1111;
else
case ( A )
3'b000 : Y<= 8'b1111_1110;
3'b001 : Y<= 8'b1111_1101;
3'b010 : Y<= 8'b1111_1011;
3'b011 : Y<= 8'b1111_0111;
3'b100 : Y<= 8'b1110_1111;
3'b101 : Y<= 8'b1101_1111;
3'b110 : Y<= 8'b1011_1111;
3'b111 : Y<= 8'b0111_1111;
endcase
end
endmodule
4、数据选择器
module mux8_1_verilog ( Y ,A ,D0, D1,
D2, D3, D4, D5, D6, D7 ,G );
input [2:0] A ; //地址输入端wire [2:0] A ;
input D0 ; //数据输入端input D1 ; //数据输入端
input D2 ; //输入端
input D3 ; //输入端
input D4 ; //输入端
input D5 ; //输入端
input D6 ; //输入端
input D7 ; //输入端
input G ; //端，当G=1=0，当G=0数据选择器正常工作wire G ;
output Y ; //数据输出端reg Y ;
always @(G or A or D0 or D1 or D2 or D3
or D4 or D5 or D6 or D7 )
begin
if (G == 1) //使能端的优先级高 Y <= 0;
else
case (A ) //根据输入的地址确定数据选择器输出输入数据 3'b000 : Y = D0 ;
3'b001 : Y = D1 ;
3'b010 : Y = D2 ;
3'b011 : Y = D3 ;
3'b100 : Y = D4 ;
3'b101 : Y = D5;
3'b110 : Y = D6 ;
3'b111 : Y = D7 ;
default : Y = 0;
endcase
end
endmodule
5、多位数值比较器
module compare_verilog ( Y ,A ,B );
input [3:0] A ; //4位二进制数wire [3:0] A ;
input [3:0] B ; //4位二进制数Bwire [3:0] B ;
output [2:0] Y ; //A与B大小比较结果reg [2:0] Y ;
always @ ( A or B )
begin
if ( A > B )
Y <= 3'b001; //A > B时Y输出3'b001 else if ( A == B)
Y <= 3'b010; //A = B时Y输出3'b010
else
Y <= 3'b100; //A < BY输出3'b100
end
endmodule
6、全加器
module sum_verilog ( A ,Co ,B ,S ,Ci );
input A ; //输入加数wire A ;
input B ; //输入加数Bwire B ;
input Ci ; //相邻低位的信号wire Ci ;
output Co ; //向相邻高位的输出信号reg Co ;
output S ; //相加和数输出reg S ;
always @ ( A or B or Ci)
begin
if ( A== 0 && B == 0 && Ci == 0 )
begin
S <= 0;
Co <= 0;
end
else if ( A== 1 && B == 0 && Ci == 0 )
begin
S <= 1;
Co <= 0;
end
else if ( A== 0 && B == 1 && Ci == 0 )
begin
S <= 1;
Co <= 0;
end
else if ( A==1 && B == 1 && Ci == 0 )
begin
S <= 0;
Co <= 1;
end
else if ( A== 0 && B == 0 && Ci == 1 )
begin
S <= 1;
Co <= 0;
end
else if ( A== 1 && B == 0 && Ci == 1 )
begin
S <= 0;
Co <= 1;
end
else if ( A== 0 && B == 1 && Ci == 1 )
begin
S <= 0;
Co <= 1;
end
else
begin
S <= 1;
Co <= 1;
end
end
endmodule
7、D触发器
module Dflipflop ( Q ,CLK ,
RESET ,SET ,D ,Qn );
input CLK ; //D触发器输入时钟wire CLK ;
input RESET ; //D触发器清零输入wire RESET ;
input SET ; //D触发器预置数输入wire SET ;
input D ; //D触发器输入wire D ;
output Q ; //D触发器输出reg Q ;
output Qn ;
wire Qn ;
assign Qn = ~Q ; //将D触发器取反always @ ( posedge CLK or negedge SET or negedge RESET )
begin
if ( !RESET) //RESET下降沿将D触发器输出清零 Q <= 0 ;
else if ( ! SET) //SER下降沿将D触发器输出置 Q <= 1;
else Q <= D; //CLK上升沿D触发器输出输入
end
endmodule
8、寄存器
module reg8 ( clr ,clk ,DOUT ,D );
input clr ; //异步清零高有效wire clr ;
input clk ; //时钟输入wire clk ;
input [7:0] D ; //寄存器数据输入wire [7:0] D ;
output [7:0] DOUT ; //寄存器数据输出reg [7:0] DOUT ;
always @ ( posedge clk or posedge clr)
begin
if ( clr == 1'b1)
DOUT <= 0;
else DOUT <= D ;
end
endmodule
9、双向移位寄存器
module shiftdata ( left_right ,load ,clr ,clk ,
DIN ,DOUT );
input left_right ; // 左移右移控制信号wire left_right ;
input load ; //异步置数信号有效时将DIN输入wire load ;
input clr ; //异步清零信号有效wire clr ;
input clk ; //时钟输入wire clk ;
input [3:0] DIN ; //并行输入wire [3:0] DIN ;
output [3:0] DOUT ; //并行输出wire [3:0] DOUT ; // DOUT是一个wire型变量不能always块被赋值
reg [3:0] data_r; //定义寄存器型data_r作为中间变量assign DOUT = data_r ;
always @ ( posedge clk or posedge clr
or posedge load )
begin
if ( clr == 1) //异步清零 data_r <= 0;
else if (load ) //异步置数 data_r <= DIN;
else begin
if ( left_right) //left_right=1，信号左移 begin
data_r <= (data_r<<1);
data_r[0] <= 0; //移出位补 end
else begin //left_right=0，信号右移
data_r <= (data_r>>1);
data_r[3] <= 0; //位补 end
end
end
endmodule
10、4位二进制加减法计数器
module counter4 ( load ,clr ,c ,DOUT ,
clk, up_down ,DIN);
input load ; //异步预置数input clk; //输入时钟wire load ;
input clr ; //异步清零wire clr ;
input up_down ; //加减计数，up_dpwn=1计数up_down=0减计数wire up_down ;
input [3:0] DIN ; //预置数输入wire [3:0] DIN ;
output c ; //进位/借位输出可以用于计数器级联reg c ;
output [3:0] DOUT ; //计数输出
wire [3:0] DOUT ;
reg [3:0] data_r;
assign DOUT = data_r;
always @ ( posedge clk or posedge clr
or posedge load)
begin
if ( clr == 1) //异步清零
data_r <= 0;
else if ( load == 1) //异步预置
data_r <= DIN;
else begin if ( up_down ==1) //加计数
begin
if ( data_r == 4'b1111) begin
data_r <= 4'b0000;
c = 1;
end
else begin
data_r <= data_r +1;
c = 0 ;
end
end
else //减计数 begin
if ( data_r == 4'b0000) begin
data_r <= 4'b1111;
c = 1;
end
else begin
data_r <= data_r -1;
c = 0 ;
end
end
end
end
endmodule
11、十进制加减法计数器
module counter10 ( load ,clr ,c ,DOUT ,clk,
up_down ,DIN ,seven_seg);
input load ; //异步预置数
input clk; 时钟
wire load ;
input clr ; //清零
wire clr ;
input up_down ; //计数，up_dpwn=1计数up_down=0减计数wire up_down ;
input [3:0] DIN ; //预置数输入
wire [3:0] DIN ;
output c ; //输出可以用于计数器级联
reg c ;
output [3:0] DOUT ; //
output [7:0] seven_seg; //7段数码管wire [3:0] DOUT ;
reg [3:0] data_r;
assign DOUT = data_r;
always @ ( posedge clk or posedge clr
or posedge load)
begin
if ( clr == 1) //异步清零
data_r <= 0;
else if ( load == 1) //异步预置
data_r <= DIN;
else if ( up_down ==1 & data_r == 9) //加进位 begin
c = 1;
data_r <= 4'b0000;
end
else if ( up_down ==0 & data_r == 0) //减借位 begin
c = 1;
data_r <= 9;
end
else
begin
if (up_down ==1) begin //加计数
data_r <= data_r +1;
c = 0 ;
end
else begin //减计数
data_r <= data_r -1 ;
c = 0 ;
end
end
end
/************数码管***************/
assign seven_seg =Y_r;
reg [7:0] Y_r;
always @(data_r ) //用7段数码管显示计数输出begin
Y_r =8'
case (data_r )
4'b0000: Y_r = 8' //显示0
4'b0001: Y_r = 8' //显示1
4'b0010: Y_r = 8' //显示2
4'b0011: Y_r = 8' //显示3
4'b0100: Y_r = 8' //显示4
4'b0101: Y_r = 8' //显示5
4'b0110: Y_r = 8' //显示6
4'b0111: Y_r = 8' //显示7
4'b1000: Y_r = 8' //显示8
4'b1001: Y_r = 8' //显示9
default: Y_r = 8' //默认数码管不发光 endcase
end
endmodule
12、顺序脉冲发生器
module pulsegen ( Q ,clr ,clk);
input clr ; //异步预置数wire clr ;
input clk ; //时钟输入
wire clk ;
output [7:0] Q ;//顺序脉冲输出wire [7:0] Q ;
reg [7:0] temp ;
reg x;
assign Q =temp;
always @ ( posedge clk or posedge clr )
begin
if ( clr==1)
begin
temp <= 8' //temp寄存预定的序列
x= 0 ;
end
else
begin
x<= temp[7] ;/序列最高位输出
temp <= temp<<1 ;/temp左移一位
temp[0] <=x; //将输出的结果赋给序列最低位，实现序列的循环输出
end
end
endmodule
13、序列信号发生器
module xlgen ( Q ,clk ,res);
input clk ; //时钟输入
wire clk ;
input res ; //异步预置数wire res ;
output Q ; //序列信号输出reg Q ;
reg [7:0] Q_r ;
always @( posedge clk or posedge res)
begin
if (res ==1)
begin
Q <= 1'b0;
Q_r <= 8' ;//Q_r寄存预定的序列 end
else
begin
Q <= Q_r[7]; //序列最高位输出 Q_r <= Q_r<<1; //Q_r左移一位 Q_r[0] <=Q; //将输出的结果赋给序列最低位，实现序列的循环输出 end
end
endmodule
14、分频器
module clockdiv ( Q ,rst ,sysclk ,sel );
input rst ; //系统复位wire rst ;
input sysclk ; //系统时钟输入wire sysclk ;
input [1:0] sel ; //分频倍数选择wire [1:0] sel ;
output Q ; //分频器输出wire Q ;
reg [2:0] q;
reg [31:0] cnt ;
reg clk ;
//时钟分频模块
always @( posedge sysclk or negedge rst)
begin
if ( !rst ) begin
cnt <= 0 ;
clk <= 1'b1 ;
end
else begin
cnt <= cnt + 1'b1 ;
if (cnt >= 32'd2500000 ) begin /clk时钟周期是系统时钟的 clk <= ~clk;
cnt <= 0 ;
end
end
end
//分频器模块
always @ ( posedge clk or negedge rst )
if ( !rst ) q[0] <= 0;
else q[0] <= ~q[0] ; // q[0]是clk的
always @ ( posedge q[0] or negedge rst )
if ( !rst ) q[1] <= 0;
else q[1] <= ~q[1] ; // q[1]是clk的4
always @ ( posedge q[1] or negedge rst )
if ( !rst ) q[2] <= 0;
else q[2] <= ~q[2] ; // q[2]是clk的8分频
assign Q = (sel== 2'd0) ? clk : //分频器输出clk (sel== 2'd1) ? q[0] : //分频器输出clk的二分频 (sel== 2'd2) ? q[1] : //分频器输出clk的四分频 (sel== 2'd3) ? q[2] : 0; //分频器输出clk的八分频endmodule
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